Memory Interface Unit (MIU)

Connects the Configurable System-on-Chip to external memory

  • Interface to 256Kx8 external memory

    • Typically FLASH (EPROM, EEPROM, SRAM also supported)

    • Holds initialization data and user's code
Memory Interface Unit block diagram Memory Interface Unit (MIU) block diagram.

  • Supports optional serial-sequential access PROM for initialization

    • Code loaded into on-chip system SRAM

    • Unused address and data lines re-used as user-defined PIO pins

  • Expands up to a 32-bit address bus

    • CSoC powers up with 18 address lines

    • Additional address lines use PIO pins

    • Used for logic expansion, multi-chip designs

  • Provides selectable read/write timing to simplify user’s design

    • Variable-speed OE-, WE-, and CE- control signals support different memories

  • Allows access to external peripherals