- Easy communication with CSL functions
- Synchronous, timely address decoding
- Eliminates or reduces logic overhead in CSL
- Decode a specific address range
- Access to a specific processor address space (code, data, SFR)
- Address size (from 1 byte to 16 Mbytes)
- Integrated, distributed resource
- One CSI Selector per every 16 CSL Cells
- Three operating modes
- Selector decodes read and write transactions to the target address range
- Chip Select provides a chip select (decodes both read or write) and a read/write direction control
- DMA Control steers DMA request/acknowledge to and from a "soft" peripheral
- Match Registers provide bit-wise decoding of the full 32-bit address space
- Match Register values automatically assigned by the Triscend FastChip Configurable System-on-Chip Development System
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