DMA Controller

Offloads data transfers from the microcontroller

  • Two independent channels for device/memory transfers

  • Transfer rates up to 40 Mbytes/second

  • Configurable System Logic (CSL) peripherals can become bus masters by controlling a DMA channel

    • The DMA channel acts as a "proxy" bus master for the CSL function.

    • The CSL peripheral re-uses the bus control logic already embedded in the DMA controller using the REQSEL and ACKSEL connections on the peripheral's DMA Control register.

  • Distributed requests/acknowledge access from within the CSL matrix
DMA Controller block diagram
DMA Controller block diagram.
  • Channel auto-initialization

  • Programmable transfer parameters

  • Interrupt capabilities

    • Transfer complete

    • Channel initialized

    • Pending Request Counter overflowed (exceeds 64K)

    • Each interrupt type separately enabled

  • Various transfer types

    • Memory-to-I/O

    • I/O-to-memory

    • Memory-to-memory (chain channels 0 and 1)

  • Block transfers

  • Software-initiated DMA requests

  • CRC checking on DMA data stream

  • Tracks pending requests, services requests when possible

  • Transfers can be terminated

  • Automatic address generation

    • Increment

    • Decrement

    • Constant address